1. Field of the Invention
The present relation relates to an interface mechanism and particularly to an interface mechanism for interfacing a real-time clock operating at a first frequency with a data processing circuit operating at a second frequency.
2. Description of the Prior Art
Many data processing circuits utilise real-time clocks to provide a real-time clock value indicating, for example, the current day, date and time. Typically, when the data processing circuit is first activated, the correct day, date and time may need to be set. When the data processing circuit is shut down, power is maintained to the real-time clock, usually by a battery, so that the real-time clock may continue to operate. However, the real-time clock value may need to be updated for various reasons such as, for example, any cumulative inaccuracies of the real-time clock, a change of time zones or the loss of power to the real-time clock. Hence, it is known to provide an interface mechanism for interfacing the real-time clock with a data processing circuit which allows the real-time clock value to be updated.
The real-time clock will generally operate at a low frequency of typically 1 Hz and may therefore provide an incremented real-time clock value to the data processing circuit once every second. The data processing circuit will often be operating at a different frequency to the real-time clock, for example 30 MHz, and hence the interface mechanism will often need to handle signals received at different frequencies.
FIG. 1 describes such a known interface mechanism. The interface mechanism, generally 100, interfaces a real-time clock, generally 110, with a data processing circuit 190. For clarity, signals issued in the data processing circuit frequency domain are annotated with the subscript f2, whilst signals issued in the real-time clock frequency domain are annotated with the subscript f1.
In overview, the data processing circuit 190 receives a real-time clock value Cf2 synchronised with the data processing circuit frequency and generated by the interface mechanism 100 in response to a real-time clock value Cf1 issued by the real-time clock 110. The data processing circuit 190 may issue an update value Wf2 and a control signal CTLf2 to the interface mechanism 100 to update the real-time clock 110. The interface mechanism 100 then updates the real-time clock 110 and once the update is complete the real-time clock 110 issues an updated real-time clock value Cf1.
The configuration of the real-time clock 110 will now be described in more detail. The real-time clock 110 comprises a multiplexer 160, a register 170 an incrementer 180 and a clock generator (not shown) for generating a 1 Hz clock signal CLKf1. The real-time clock 110 is clocked by the 1 Hz clock signal CLKf1. The register 170 is coupled to the clock generator, the multiplexer 160 and the incrementer 180. The register 170 stores the real-time clock value representing, for example, a time and date. The register 170 receives the clock signal CLKf1 from the clock generator and the output from the multiplexer 160. The output of the multiplexer 160 is loaded into, and output by, the register 170 each time the register 170 is clocked by the clock signal CLKf1 (e.g. on the rising edge of the clock signal). The incrementer 180 receives the output of the register 170, increments the value by one and outputs the incremented value to the multiplexer 160. When the register 170 is next clocked, the incremented value will be loaded from the multiplexer 160 into the register 170 and output to the incrementer 180.
The multiplexer 160 allows the real-time clock value to be incremented or updated. The multiplexer 160 receives the output of the incrementer 180 at one input and the output from the interface mechanism 100 at the other input. The multiplexer 160 is controlled by a signal LOAD received from the interface mechanism 100. When the signal LOAD is asserted the multiplexer 160 outputs the value received from the interface mechanism 100, whilst when the signal LOAD is not asserted the multiplexer 160 outputs the value received from the incrementer 180. Hence, in the absence of the signal LOAD, the value in the register 170 is incremented every second and output as the real-time clock value Cf1. When the signal LOAD is asserted, the update value W from the interface mechanism 100 is loaded into the register 170 when clocked by the clock signal CLKf1 and output as the updated the real-time clock value Cf1.
The configuration of the interface mechanism 100 will now be described in more detail. The interface mechanism 100 comprises a state machine 120, a register 130 and a register 140. The interface mechanism 100 is clocked by a clock signal CLKf2. The state machine 120 is coupled to the data processing circuit 190, the real-time clock 110, the register 130 and the register 140. The state machine 120 controls the register 130, the register 140 and the multiplexer 160.
The state machine 120 receives the clock signal CLKf2 and a control signal CTLf2 from the data processing circuit 190. The state machine 120 monitors the clock signal CLKf1 issued by the clock generator of the real-time clock 110. The state machine 120 will assert a signal LOAD1 to the register 130 and a signal LOAD2 to the register 140 in response to the control signal CTL,f2 indicating that an update should take place. The register 130 is coupled to the data processing circuit 190, the state machine 120 and the register 140. The register 130 receives the update value Wf2 from the data processing circuit 190.
When the signal LOAD1 is asserted the update value Wf2 will be loaded into. and output by, the register 130. The contents of register 130 are output to the register 140. The register 140 is coupled to the register 130, the state machine 120 and multiplexer 160 of the real-time clock 100. The register 140 receives the update value W from the register 130. When the signal LOAD2 is asserted the update value W will be loaded into, and output by, the register 140. The contents of register 140 are output to the multiplexer 160.
Sync logic 150 is coupled to the output of the register 170 and to the data processing circuit. Sync logic receives the real-time clock value Cf1 output from the register 170 at the frequency f1 and transforms this to a real-time clock value Cf2 having the same value but synchronised with the frequency f2.
The operation of the interface mechanism 100 and real-time clock illustrated in FIG. 1 will now be described in more detail with reference also to FIG. 2.
During normal operation of the real-time clock 110, the register 170 may be activated with a value representing a time, day and date which is output as the real-time clock value Cf1. The real-time clock value Cf1 n is transformed by the sync logic 150 and output as a real-time clock value Cf2 which is received by the data processing circuit 190. As mentioned earlier, the real-time clock value Cf1, is incremented every second when the register 170 is clocked by the clock signal CLKf1.
The real-time clock value Cf1 may be updated by the interface mechanism 100 in response to signals issued by the data processing circuit 190.
In order to initiate the update of the real-time clock 110, a control signal CTLf2 and an update value W2 are issued by the data processing circuit 190 to the state machine 120 shortly after a rising edge of the clock signal CLKf2. In response, the state machine 120 issues a signal LOAD1 to the register 130. The register 130 will then load and output the update value Wf2 when clocked by the next clock signal CLKf2.
The state machine 120 will then determine the state of the signal LOAD. If the signal LOAD is asserted then this indicates that a previous update of the real-time clock 110 has not yet completed. Assuming the signal LOAD is not asserted, then shortly after the rising edge of the next clock signal CLKf2 the state machine 120 issues a signal LOAD2 to the register 140 as indicated in FIG. 2. The register 140 will then, when clocked by the clock signal CLKf2, load and output the update value W which is presented as an input to the multiplexer 160. If the signal LOAD is asserted, then the state machine 120 will wait until the signal LOAD is not asserted before issuing the signal LOAD2.
Assume that prior to the issue of the control signal CTLf2 indicating that an update should take place, the real-time clock value Cf1 has the value X. As described above, in the absence of the signal LOAD, the value output by the multiplexer 160 will be X+1. The state machine 120 and the register 170 wait until the next clock signal CLKf1 is received from the clock generator. On the rising edge of the clock signal CLKf1, the register 170 loads the output of the multiplexer 160 and the real-time clock value Cf1 has the value X+1. The output of the register 170 is incremented by the incrementer 180 and presented to the multiplexer 160 which, in the absence of the signal LOAD, outputs a value of X+2.
Once the state machine 120 has received the clock signal CLKf1, it knows that it is now safe to issue the signal LOAD to the multiplexer 160 without the risk of conflicting with the increment operation of the real-time clock 110, and hence the state machine 120, on the rising edge of the next clock signal CLKf2 following the clock signal CLKf1, asserts and holds the signal LOAD to the multiplexer 160.
Accordingly, the update value W is presented as the output of the multiplexer 160. On the rising edge of the next clock signal CLKf1, the update value W is loaded into the register 170 and the real-time clock value Cf1 has the value W. The output of the register 170 is incremented and presented to the multiplexer 160 which, due to the continued assertion of the signal LOAD still outputs the value W. On the rising edge of the next clock signal CLKf2 after the clock signal CLKf1, the state machine 120 stops asserting the signal LOAD to the multiplexer 160 since the reception of the clock signal CLKf1 by the state machine 120 indicates that the update has completed, and the multiplexer 160 then outputs the value W+1.
Hence, the period between when the control signal CTLf2 is first issued and the real-time clock value Cf1 has the updated value W is between one and two seconds. This latency between the update being requested and the update value being output is undesirable because the circuitry must operate for over a second after the write has been initiated to ensure correct operation. In situations where the circuitry loses power due to accidental or intentional power down during the update the status of the real-time clock may be unclear, at worst the update may not occur.
One possible solution to reduce the latency problem would be to provide certain circuit elements which could be clocked at either of the two frequencies, for example register 170 could be designed to be clocked at either frequency. However, it will be appreciated by those skilled in the art that this approach is likely to lead to reusability problems.
Thus an interface mechanism is required which can reduce the latency effect and effect the update in a shorter time period without affecting reusability.
According to a first aspect of the present invention there is provided an interface mechanism for interfacing a real-time clock operating at a first frequency with a data processing circuit operating at a second frequency comprising a first input for receiving a relative real-time clock value from the real-time clock; a second input for receiving an update value from the data processing circuit specifying a desired value for the real-time clock; update logic for producing an absolute real-time clock value, the update logic being arranged in response to receipt of the update value to generate an offset value derived from the relative real-time clock value and the update value, the offset value then being applied to the relative real-time clock value to produce an updated absolute real-time clock value, and an output for issuing the updated absolute real-time clock value.
Hence, the latency problem is reduced as a real-time clock value may be updated much more quickly, typically in less than two cycles of the second frequency. This increased speed is achieved by removing the need to write the update value to the real-time clock, the entire update process instead occurring in the second frequency domain. In accordance with the invention, the interface mechanism operating at the data processing circuit frequency generates an offset value derived from the relative real-time clock value and the update value. When the relative real-time clock value is received by the interface mechanism, this offset value is applied to the relative real-time clock value to produce the updated absolute real-time clock value for outputting to the data processing circuit.
Preferably, the offset value is derived by calculating the difference between the relative real-time clock value and the update value; and the updated absolute real-time clock value is produced by calculating the difference between the relative real-time clock value and the offset value.
Hence, the offset value will only need to be calculated each time that an update is requested by the data processing circuit. Once the offset value has been calculated it can be applied to a changing relative real-time clock value to produce a correct updated absolute real-time clock value.
Preferably, the update logic further comprises a first arithmetic unit for generating the offset value by subtracting the update value from the relative real-time clock value; and a second arithmetic unit for generating the updated absolute real-time clock value by subtracting the offset value from relative the real-time clock value.
Hence, the offset value and the updated absolute real-time clock value may be generated by a simple arithmetic subtraction operation, both operations being relatively quick to perform.
Preferably, the update logic is triggered to perform an update of the absolute real-time clock value in response to a control signal received from the data processing circuit in addition to the update value the offset value being derived in a second frequency clock cycle following receipt of the control signal, and the updated absolute real-time clock value being produced in the next occurring second frequency clock cycle.
Hence, the data processing circuit may indicate to the interface mechanism when an update is required. This allows a data bus to be used to issue the update value to the interface mechanism, and once the update value has been received by the interface mechanism the data bus is then available for other operations.
Preferably, the update logic further comprises a state machine for receiving the control signal and a second frequency clock signal wherein: in response to the control signal, a first signal is issued by the state machine during a first second frequency clock cycle to cause the first arithmetic unit to generate the offset value, and in response to the next occurring second frequency clock cycle, a second signal is issued by the state machine causing the second arithmetic unit to generate the updated absolute real-time clock value.
Hence, the state machine may control the generation of the offset value and the updated absolute real-time clock value. The state machine initiates the generation of the offset value by the first arithmetic unit during a first clock cycle in response to the control signal received from the data processing circuit. On the next occurring clock cycle, which allows time for the offset value to be generated by the first arithmetic unit, the updated absolute real-time clock value is generated.
Preferably, the update logic further comprises: a first register for storing and outputting to the first arithmetic unit the update value from the data processing circuit in response to the first signal from the state machine; and a second register for storing and outputting to the second arithmetic unit the offset value generated by the first arithmetic unit in response to the second signal.
Hence, by storing the updated value the data processing circuit may be decoupled from the interface mechanism, thereby allowing the data processing circuit to perform other operations. Also, by storing the offset value, this value need not be recalculated each time the updated absolute real-time clock value is generated.
Preferably, the interface mechanism further comprises sync logic for synchronising the relative real-time clock value generated by the real-time clock with the second frequency, wherein the update logic receives the resynchronised relative real-time clock value.
Hence, the update logic may be provided with the relative real-time clock value synchronised with the frequency used by the data processing circuit.
According to a second aspect of the present invention there is provided a method of interfacing a real-time clock operating at a first frequency with a data processing circuit operating at a second frequency, comprising the steps of, receiving a relative real-time clock value from the real-time clock; receiving an update value from the data processing circuit specifying a desired value for the real-time clock; producing an updated absolute real-time clock value by generating an offset value derived from the relative real-time clock value and the update value and by applying the offset value to the relative real-time clock value; and issuing the updated absolute real-time clock value.
According to a third aspect of the present invention there is provided a computer-readable medium having stored thereon a plurality of instructions, the plurality of instructions including instructions which, when executed by an interface mechanism, cause the interface mechanism to implement a method for interfacing a real-time clock operating at a first frequency with a data processing circuit operating at a second frequency the method comprising the steps of: receiving a relative real-time clock value from the real-time clock; receiving an update value from the data processing circuit specifying a desired value for the real-time clock; producing an updated absolute real-time clock value by generating an offset value derived from the relative real-time clock value and the update value and by applying the offset value to the relative real-time clock value; and issuing the updated absolute real-time clock value.